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Denis Flandre   Professor  Senior Scientist or Principal Investigator 
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Denis Flandre published an article in April 2019.
Top co-authors See all
N. Collaert

276 shared publications

Imec, B-3001 Leuven, Belgium

Laurent A Francis

105 shared publications

Electrical Engineering Department, Universite Catholique de Louvain, Microsystems Chair, Place du Levant, 3, Maxwell Building, B-1348 Louvain-la-Neuve, BELGIUM, Louvain-la-Neuve, 1348, BELGIUM

Santiago Celma

72 shared publications

Electronics and communications engineering, Universidad de Zaragoza, Spain ()

Valeriya Kilchytska

57 shared publications

Université Catholique de Louvain, Louvain-la-Neuve, Belgium

Jean-Pierre Raskin

54 shared publications

Institute of Information and Communication Technologies, Electronics and Applied Mathematics (ICTEAM), Universitè Catholique de Louvain (UCL), 1348 Louvain-la-Neuve, Belgium

Publication Record
Distribution of Articles published per year 
(1988 - 2019)
Total number of journals
published in
Publications See all
PREPRINT 0 Reads 0 Citations Detection mechanism in highly sensitive ZnO nanowires network gas sensors Nohora Caicedo, Renaud Leturcq, Jean-Pierre Raskin, Denis Fl... Published: 09 April 2019
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Metal-oxide nanowires are showing a great interest in the domain of gas sensing due to their large response even at a low temperature, enabling low-power gas sensors. However their response is still not fully understood, and mainly restricted to the linear response regime, which limits the design of appropriate sensors for specific applications. Here we analyse the non-linear response of a sensor based on ZnO nanowires network, both as a function of the device geometry and as a response to oxygen exposure. Using an appropriate model, we disentangle the contribution of the nanowire resistance and of the junctions between nanowires in the network. The applied model shows a very good consistency with the experimental data, allowing us to demonstrate that the response to oxygen at room temperature is dominated by the barrier potential at low bias voltage, and that the nanowire resistance starts to play a role at higher bias voltage. This analysis allows us to find the appropriate device geometry and working point in order to optimize the sensitivity. Such analysis is important for providing design rules, not only for sensing devices, but also for applications in electronics and opto-electronics using nanostructures networks with different materials and geometries.
Article 0 Reads 0 Citations Ultra Low-Loss Si Substrate for On-Chip UWB GHz Antennas N. Andre, M. Rack, L. Nyssens, C. Gimeno, D. Oueslati, K. Be... Published: 01 January 2019
IEEE Journal of the Electron Devices Society, doi: 10.1109/jeds.2019.2902636
DOI See at publisher website ABS Show/hide abstract
In this paper, measurements and simulations of miniature monopole antennas for ultra-wideband GHz intra-and inter-chips communication and biomedical applications are presented. Folded designs on four substrates are studied: standard bulk, high-resistivity bulk, ultra low-loss radiofrequency Silicon-on-Insulator (RF SOI) and quartz. Among the Si-based substrates, RF SOI with its trap-rich sublayer demonstrates the best performances with the lowest RF power losses and centimetric transmission distance between antennas. Transmitted power between two antennas was measured from 0.01 to 20 GHz. Using substrate characterization of resistivity, permittivity and loss tangent based on measured CPW lines on the same substrates, good agreement is obtained between the return losses of simulated antennas on each substrate and numerical solutions, confirming the impact of the substrate properties. An antenna bandwidth of 680 MHz is demonstrated at 6.0 GHz meeting the criterion for UWB radio communications in the 6-10 GHz band.
Article 0 Reads 0 Citations Analysis of Mismatching on the Analog Characteristics of GC SOI MOSFETs Camila Alves, Denis Flandre, Michelly De Souza Published: 12 December 2018
Journal of Integrated Circuits and Systems, doi: 10.29292/jics.v13i3.16
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This paper presents an evaluation of mismatching impact on the analog characteristics of fully-depleted graded-channel (GC) SOI MOSFET. This study is carried out by means of electrical measurements and two-dimensional numerical simulations, comparing GC to uniformly doped transistors. Important basic parameters such as threshold voltage and subthreshold slope were analyzed as well as analog parameters, namely transconductance, output conductance, Early voltage and intrinsic voltage gain.
PROCEEDINGS-ARTICLE 3 Reads 0 Citations Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT smart sensors Pengcheng Xu, Denis Flandre, David Bol Published: 01 November 2018
2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), doi: 10.1109/asscc.2018.8579281
DOI See at publisher website
PROCEEDINGS-ARTICLE 0 Reads 0 Citations A Transient Noise Analysis of Secured Dual-Rail Based Logic Style Kashif Nawaz, Itamar Levi, Francois-Xavier Standaert, Denis ... Published: 01 November 2018
2018 New Generation of CAS (NGCAS), doi: 10.1109/ngcas.2018.8572199
DOI See at publisher website
Article 0 Reads 0 Citations Influence of Geometrical Parameters on the DC Analog Behavior of the Asymmetric Self-Cascode FD SOI nMOSFETs Michelly De Souza, Rafael Assalti, Denis Flandre Published: 05 October 2018
Journal of Integrated Circuits and Systems, doi: 10.29292/jics.v13i2.15
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This paper assesses the DC analog performance of a composite transistor named Asymmetric Self-Cascode structure, which is formed by two Fully Depleted SOI nMOSFETs connected in series with shortened gates. The influence of geometrical parameters, such as different channel widths and lengths on the transistors at source and drain sides is evaluated through three-dimensional numerical simulations, which have been firstly adjusted to the experimental measurements. The transconductance, output conductance, Early voltage and intrinsic voltage gain have been used as figure of merit to explore the advantages of the composite transistor. From the obtained results, the largest intrinsic voltage gain has been obtained by using longer channel lengths for both transistors, with narrower device close to the source and wider transistor near to the drain.