DESIGN OF LOW POWER PHASE LOCKED LOOP

The phase-locked loop is am important system that has contributed significantly to technological advancements in many applications in the ever so fast-evolving digital era. In this paper, a PLL is designed using 90 nm CMOS technology node with 1.8V supply voltage. It features a PLL design with power consumption as low as 194.26µW with better transient analysis and DC analysis in an analog-to-digital environment. The proposed PLL design provides the best solution for many applications where a PLL is required due to its high performance but has to be accommodated in less area and low power consumption than state-of-the-art methods .