A High Level Synthesis Approach for a RISC-V RV32I Based SoC and its FPGA Implementation using Open Source Tools

In this paper, we present a RISC-V RV32I based System on Chip (SoC) design approach using High Level Synthesis (HLS) tools. The proposed approach consists of three separate levels: The first one is an HLS design and simulation purely in C++. The second one is a Verilog simulation of the HLS generated Verilog implementation of the CPU core, a RAM unit initialized with a short assembly code, and a simple output port which simply forwards the output data to the simulation console. Finally, the third level is an implementation and testing of this SoC on an FPGA board running at a clock speed of 100 MHz. A sample C code is compiled using the GNU RISC-V compiler tool chain and tested on the HLS generated RISC-V RV32I core as well. The HLS design consists of a single C++ file with less than 300 lines, a single header file, and a testbench in C++. Our design objectives are (1) The C++ code should be easy to read for an average engineer, and (2) The coding style should dictate minimal area and minimal resource utilization without significantly degrading the code readability. The proposed system is implemented for two different I/O bus alternatives: (1) A traditional single clock cycle delay memory interface, and (2) The industry standard AXI bus. We present timing closure, resource utilization, and power consumption estimates. Furthermore, by using the open-source synthesis tool Yosys, we generate a CMOS gate-level design and provide gate count details. All design, simulation, and constraint files are publicly available in a GitHub repo. We also present a simple dual-core SoC design, but detailed multi-core designs and other advanced futures are planned for future research.