Single-Layer Parity Generator and Checker Design Using XOR Gate in Quantum dot Cellular Automata (QCA)

Quantum-Dot Cellular Automata (QCA) emerges as a promising nanotechnology, offering a viable alternative to traditional technologies for high-performance, low-power computing at high operating speeds in a compact area. It is well known that parity generators and checkers are crucial components in processors and communication circuits. In line with recent trends in nanocircuits in electronics, this work designs a parity generator and checker using QCA, an emerging nanotechnology that is gaining popularity for nanocomputing tasks. This paper presents a dual-tasking QCA-based 3-bit parity generator and checker, implemented using an optimized modified majority voter (MMV)-based XOR gate in QCA circuitry. It is a dual-tasking circuit, as the single circuit can both generate and check parity. The efficient XOR gate design significantly enhances the reliability and importance of parity checker circuits in QCA, which is vital for error detection in communication systems. A full input–output-accessible,single-layer and scalable layout was designed and simulated using QCADesigner 2.0.3 without incorporating crossovers to minimize fabrication complexity. Detailed power dissipation analysis, conducted using two tools, QCADesigner-E and QCAPro, shows that the circuit consumes 23.86 meV, demonstrating 86% energy efficiency as well as 59% area efficiency compared to the latest reported QCA-based parity checkers. The proposed circuit exemplifies a significant advancement in nanocomputing, providing a scalable, energy-efficient solution for next-generation computing systems, further establishing QCA as a key technology for future low-power, high-density applications.