Exploring the Impact of Key Design Parameters on Double-Gate TFET Performance for Low-Power Applications

Tunnel Field-Effect Transistors (TFETs) are being widely explored for ultra-low-power VLSI because their band-to-band tunnelling (BTBT) transport permits subthreshold swings (SSs) below the 60 mV/dec thermionic limit at room temperature, along with significantly lower leakage than MOSFETs. This paper presents a systematic TCAD study of Double-Gate (DG) TFETs, which maps how four primary knobs—gate dielectric material, silicon channel thickness, gate length, and source and drain doping—shape the following key figures of merit: ON-current (ION), OFF-current (IOFF), threshold voltage (VTH), SS, and the ION/IOFF switching ratio. High-κ gate enhances gate-to-channel coupling and boosts tunnelling efficiency; rigorous body scaling enhances electrostatic control; and targeted source-proximal doping profiles elevate ION while minimising leakage. We also measure the trade-offs between ION, SS, and IOFF that occur when scaling is completed at the same time. This shows that careful coordination is needed instead of simply tuning one parameter. This is a simulated work; the physical models are calibrated to experimental TFET data, and all parameters were checked against previously reported results. The device reaches SS = 31.4 mV/dec, VTH = 0.46 V, ION = 5.91 × 10⁻⁵ A, and an ION/IOFF of about 4.5 × 10¹¹. This shows that it can switch quickly with little leakage. The design insights that come from this work can provide useful advice on how to choose gate dielectric materials, structures, and doping strategies so that DG-TFETs can be included in the next generation of low-power semiconductor technologies.