A Deterministic Fixed-Point Multiplier-Less ANN Architecture with Zero-Activity Suppression for FPGA-Based Image Classification

Multiplier-less feed-forward Artificial Neural Networks (ANNs) are attractive for FPGA-based image classification because they avoid hardware multipliers and reduce computational complexity. However, their processing latency depends on the magnitude of the input data, since multiplication is performed through repeated accumulation of the corresponding weights. For the 196-16-10 ANN evaluated on the MNIST handwritten-digit dataset, the baseline multiplier-less architecture can require approximately 4.64 × 10^14 clock cycles per image, making its timing unsuitable for real-time imaging applications.

This work presents a deterministic fixed-point multiplier-less ANN architecture that eliminates data-dependent latency through a fixed bit-serial processing schedule. Each input bit is processed according to a predetermined sequence, ensuring a constant processing time independent of input magnitude. A zero-activity suppression mechanism is also introduced to disable accumulator updates when the current input bit is inactive, reducing unnecessary switching activity. The architecture is implemented in Verilog and evaluated through cycle-accurate Icarus Verilog simulation and Vivado synthesis on a Xilinx Artix-7 xc7a100t FPGA.

Simulation results demonstrate a fixed latency of 2166 clock cycles per image across multiple MNIST test inputs, reducing the processing-cycle count by approximately 2.1 × 10^11 relative to the baseline. Vivado synthesis reports 3549 LUTs and 3028 flip-flops, compared with 2670 LUTs and 3095 flip-flops for the baseline, representing a 32.9% increase in LUT utilization and a 2.2% reduction in flip-flop utilization. Neither design uses DSP or block RAM resources. The proposed implementation achieves 92.66% classification accuracy, within 0.17% of the baseline. At 100 MHz, the fixed latency enables approximately 46,000 image classifications per second with a guaranteed processing time for every image, demonstrating the suitability of the architecture for FPGA-based real-time image classification.