Layered transition metal chalcogenides (TMDCs) are promising materials for developing multifunctional and compact optoelectronic-integrated devices to extend Moore's Law. However, the low photoluminescence quantum efficiency (PLQY) and single carrier polarity remain two bottlenecks in achieving these exciting applications, due to the notorious defects that unavoidable in the sample preparation.Here, we report a unique defect engineering strategy from both theoretical and experimental perspectives, and achieve simultaneously giant photoluminescence enhancement and carrier polarity modulation in WS₂ monolayers via doping with IIIA atoms. The doped samples exhibit large sizes (~614 µm), significantly improved PL quality with the PL intensity/PLQY being up to two orders of magnitude higher than that of undoped ones, and simultaneous carrier polarity modulation from unipolar to ambipolar. Moreover, the constructed p-n homojunctions based on the doped samples show excellent rectification ratio (up to ~2200) and ultra-fast response time (<1 ms). Intriguingly, both the PL property and device performance display extraordinary stability even after hundreds of days under the atmospheric environment. Our doping strategy is universally applicable to other TMDCs and dopants. This work not only provides a general strategy to eliminate the negative effects of defects in 2D materials, but also utilize them to achieve desired optoelectronic properties by smart design, marking an important step toward multifunctional and high-performance optoelectronic-integrated devices and systems.

Heterostructures with the configuration of two-dimensional (2D) p-n type semiconductors have been widely studied since they not only combine the advantages of the constituent materials, but also generate new phenomena, such as the formation of built-in electric fields that help separate photogenerated carriers, suppress dark current to improve the sensitivity of photodetector, and exhibit negative differential transconductance (NDT). Inspired by these works, we have chosen the emerging p-type semiconductor tellurium (Te), which has excellent air stability and can be used for infrared photodetection, and the typical n-type semiconductor MoS₂, to form a heterojunction. Due to the built-in electric field between Te and MoS₂, as well as the formation of Schottky barrier between Te and electrode materials, the device exhibits negative/positive photoresponse under visible and infrared light, respectively, without external bias, showcasing the potential for optical encoding communication. Moreover, this self-driven photodetector performs the photoresponsivities of 1.51 A/W and 642.92 mA/W under 520 nm and 1550 nm illumination, respectively, with millisecond level response speeds. In addition, the Te/MoS2 heterostructure displays the NDT phenomena which can be used to implement as a simple CMOS inverter and the inverter can be turned off under illumination. In summary, our work has achieved wavelength-tunable positive /negative optical response as well as light switchable inverters on devices with the same structure, promoting the compactness of integrated components and expanding research on Te and its application fields.

Aluminium nitride (AlN), compared with other piezoelectric materials, has the advantages of high acoustic velocity, low loss and high temperature stability. Meanwhile, it is CMOS compatible, which can be a promising candidate for preparing high-performance piezoelectric acoustic devices. However, AlN thin film suffered from low piezoelectric coefficient and electromechanical coupling coefficient，which was not conducive to the application of high frequency filter. To solve this problem, AlN doped with Sc was proved an effective scheme for significantly increasing its piezoelectric coefficient (d₃₃) and electromechanical coupling coefficient (K_t²).

This report focuses on the key technologies of fabrication of wafer-level Al_1-xSc_xN stack layer for SMR-BAW application. The 8-inch Al_1-xSc_xN ( x ranges from 9.9% to 20.5%) film was sputtered on Si-based stack layers, consisted of SiO₂/W bragger reflector and AlN seed layer. With the increase of Sc doping content, the growth of Al_1-xSc_xN stack will be faced with the risk of crystallization degradation, stress loss and worse roughness. By employing cluster PVD equipped with tailor-made parts and stress uniformity control, we designed, fabricated and characterized high-quality wafer-level Al_1-xSc_xN stack layer which is satisfied with 5G filter applications.

By constructing a metal oxide semiconductor capacitor (MOSCAP) structure and embedding the optical waveguide, the carrier accumulation modulator allows the free carriers to accumulate on both sides of the dielectric layer, providing a large modulation bandwidth while maintaining a high modulation efficiency, and also allowing a smaller size and lower driving voltage. Meanwhile，the speed of MOSCAP modulator based on carrier accumulation is no longer limited by the carrier lifetime, but depends on the capacitance and resistance of the device structure, which is the advantage of MOSCAP modulator over carrier injection modulator and more attractive to the next generation of optical communication.

This paper aims to solve the problems of high transmission loss of optical modulators based on MOSCAP structure and the relationship between capacitance value and modulation efficiency. When the bias voltage is applied to the lower electrode and gate of the MOSCAP, the charge accumulation occurs on the lower electrode and gate, which affects the effective refractive index of the material at the rib waveguide location through the plasma dispersion effect.

Floorplanning is a critical step in realizing the physical structure of circuits, directly impacting the performance, size, yield, and reliability of Very Large Scale Integration (VLSI) circuits. Experience shows that fixed-outline problems are more complex, and fixed-outline requirements have become essential in modern layout design. However, VLSI layout planning is an NP-hard problem, necessitating more efficient and concise methods to address it. This paper improves upon the traditional complex representation mechanism based on sequence pairs by proposing a more efficient Single Sequence Layout (SSL) representation. Compared to the original dual-sequence approach, SSL simplifies the data structure, making sequence operations more convenient and efficient. Additionally, SSL demonstrates advantages over dual-sequence representations when integrated with other optimization algorithms. For solving strategies, this paper introduces a meticulously designed improved genetic algorithm, which includes a modified mutation method tailored for the single-sequence and a novel crossover operation that preserves parental characteristics. The proposed method was tested on two sets of circuits, MCNC and GSRC, and compared with methods in existing literature. Experimental results indicate that using SSL combined with the redesigned genetic algorithm achieves a certain improvement in layout success rates. With a dead space rate of 15%, the layout success rate can reach 100%, verifying the feasibility of the SSL algorithm.

The finite-time control problem of the conversion mode for tilt-rotor aircraft is investigated by a hierarchical design scheme. First, in view of the trimming solutions, the nonlinear model is transformed into a linear switched system related to the system parameters to simplify the control design. Second, a new sequential layered switching mechanism is proposed with time-dependent law of outer layer system and state-dependent law of inner layer system, which releases the requirements of initial conditions and leads to a better tracking performance. Moreove, the inherent interval for each subsystem effectively avoids the Zeno behavior. Finally, the simulation result about XV-15 aircraft is illustrated to show the effectiveness of the proposed method.

Gallium Nitride (GaN) high electron mobility transistors (HEMTs) have garnered significant attention in micro/millimeter wave and terahertz technologies due to their unique material properties, including a wide bandgap, high charge density, high electron mobility, and high-temperature tolerance. To maintain fast evolution of communication toward terahertz frequencies, the key to HEMTs based on AlGaN/GaN heterojunction is the fabrication of nanoscale T-shape gates. Implementing a floating T-gate structure through electron beam lithography (EBL) has been explored to enhance the frequency performance of GaN HEMTs. But the fabrication of T-Gate through EBL is extremely inefficient and costly. A new technology has been developed based on the conventional 248 nm lithography machine and the self-developed resolution enhancement lithography technology assisted by chemical shrink (RELACS), so that traditional optical lithography could be used to manufacture T-gates with a L_g less than 100 nm, including floating T-gates. We believe that this technology would bring new revolution for the manufacture technology of T-gate structures in GaN HEMT devices.

Through-silicon via (TSV) technology is significantly important in the three-dimensional integrated circuit (3D-IC), aiming to minimize the connection distance, reduce energy consumption, and improve integration density. To increase the stacking chip layers and the mechanical reliability, it is essential to develop TSVs with the nano-scale diameters, i.e. nano-TSV. Nano-TSVs are sub-micron Cu-filled vias, that can provide an option for efficient power delivery network through the backside of device wafers. The use of nano-TSVs helps to free up space on the wafer front-side. In high-performance compute and AI hardware, nano-TSVs can also enable a significantly higher density of interconnects and thus increase data bandwidth between wafers that are directly bonded together. Another potential application of nano-TSV is in improving the efficiency of power delivery networks. While the formation of nano-TSV still faces many process challenges. The fatal technology is the scallop pattern resulting from the Bosch etch process. The isolation and barrier liner materials with high step coverage and lower temperature deposition on the smooth surface are also necessary. The last is obtaining high-quality void-free electroplating Cu filled nano-TSV via. In this talk, we described the use of a process flow for the nano-TSV formation. A small scallop etching process has developed for the nano-TSV. High step coverage of ALD SiO₂ isolation layer, PVD Ta/TaN barrier layer and Cu seed layer. And finally, void-free Cu filling nano-TSVs with diameter of ~0.5 µm, pitch of 1.5µm and aspect ratio around 10 have been successfully demonstrated. Thus, the nano-TSV fabrication process flow is established as viable for 3D-IC applications.

Power systems are the infrastructure of modern society, and their stability is crucial for the operation of the economy and society. In the face of emergencies such as natural disasters or equipment failures, effective information exchange and rapid decision-making become particularly critical. Existing dialogue systems have many limitations when dealing with power emergency dialogues, especially in intent recognition and slot filling. To improve the performance of dialogue systems, this study proposes a multidimensional span information analysis method based on part-of-speech tagging (MSLA). This method utilizes BERT embeddings and part-of-speech tagging information to enhance the understanding of grammatical structure and semantic relationships in dialogue systems, effectively combining the advantages of pre-trained language models and detailed information from part-of-speech tagging. Experiments show that MSLA achieves better performance than existing models in both intent detection and slot filling tasks, especially on the self-built power emergency dataset, demonstrating its potential for practical application in specific domains.

With the rapid development of information technology, the efficiency and accuracy of emergency response mechanisms are of great significance for reducing disaster losses and ensuring the safety of people's lives and property. This article aims to explore the automatic generation and delivery of emergency information in power grids and power systems, and study how to realize the automatic generation and delivery of emergency information through the mining and analysis of emergency indicators and data, combined with business rules. On this basis, this paper proposes an emergency information generation model based on Transformer and joint attention mechanism and builds an emergency information reporting platform. Compared with previous work, this work has two innovations. One is to use the Pearson correlation coefficient to screen emergency indicators to reduce the amount of data required for information generation. The second is to introduce external knowledge and combine it with a joint attention mechanism to screen the knowledge, and at the same time add emergency degree recognition to generate power emergency information that is accurate and can intuitively display the degree of emergency. Through experimental verification, it can be seen that the generation method proposed in this article can accurately and concisely generate emergency information, and the reporting platform has good emergency information classification capabilities. This study can improve the efficiency of emergency information processing, ensure the timeliness and accuracy of information, and provide strong support for natural disaster emergency management decisions in power systems.