An FPGA based hardware accelerator for bio-signal digital filtering in a neonatal heart rate monitoring system employing electric potential sensors (EPS) is presented. These active sensors provide a non-contact alternative to traditional ECG electrodes, but are more susceptible to noise such as power line interference and motion artefacts, therefore additional filtering capacity is required.

The proposed system contains a single hardware filter stage for antialiasing, with the remaining digital signal processing required to provide a clinical standard ECG performed on an FPGA (National Instruments myRIO 1900). This is compared with a previous microprocessor version (Raspberry Pi 3, BCM2837 processor) containing a dual hardware/software filtering scheme, with the aim of simplifying the analog front end and allowing for reconfigurable filtering in the digital domain. A custom neonate phantom was employed to emulate real world conditions and ambient noise.

The developed FPGA system was shown to have a signal quality comparable with the microprocessor implementation, with an average signal to noise ratio loss of 2%. A 12 dB increase in attenuation of the predominant 50 Hz noise and a 90% reduction in energy per sample filtered was shown compared to the microprocessor version, indicating both efficiency and filter effectiveness gains. The proposed system accurately calculated the heart rate of a simulated neonatal ECG signal, with lower heart rate variation than the microprocessor system. Finally, the phantom was used to broadcast data from the preterm infant cardio-respiratory signals database (PICSDB) and the FPGA filtering scheme was shown to remove the majority of the ambient 50 Hz noise with an average reduction of 30 db, and provide a clean ECG signal.

These results demonstrate that FPGA filtered EPS ECGs have comparable signal quality to the combined HW/SW filtering implementation, with a reduction in complexity and power consumption.