Through-silicon via (TSV) technology is significantly important in the three-dimensional integrated circuit (3D-IC), aiming to minimize the connection distance, reduce energy consumption, and improve integration density. To increase the stacking chip layers and the mechanical reliability, it is essential to develop TSVs with the nano-scale diameters, i.e. nano-TSV. Nano-TSVs are sub-micron Cu-filled vias, that can provide an option for efficient power delivery network through the backside of device wafers. The use of nano-TSVs helps to free up space on the wafer front-side. In high-performance compute and AI hardware, nano-TSVs can also enable a significantly higher density of interconnects and thus increase data bandwidth between wafers that are directly bonded together. Another potential application of nano-TSV is in improving the efficiency of power delivery networks. While the formation of nano-TSV still faces many process challenges. The fatal technology is the scallop pattern resulting from the Bosch etch process. The isolation and barrier liner materials with high step coverage and lower temperature deposition on the smooth surface are also necessary. The last is obtaining high-quality void-free electroplating Cu filled nano-TSV via. In this talk, we described the use of a process flow for the nano-TSV formation. A small scallop etching process has developed for the nano-TSV. High step coverage of ALD SiO₂ isolation layer, PVD Ta/TaN barrier layer and Cu seed layer. And finally, void-free Cu filling nano-TSVs with diameter of ~0.5 µm, pitch of 1.5µm and aspect ratio around 10 have been successfully demonstrated. Thus, the nano-TSV fabrication process flow is established as viable for 3D-IC applications.