Nanomaterials Webinar | Breaking Moore’s Law Barrier: Transistors for Three-Dimensional Brain-Mimicking IC Architecture
the chair
The delay and power consumption are the major limitation for advanced microprocessor, even though the device will soon reach Hyper-EUV lithography and quantum-mechanical downscaling limits. To address these issues, we pioneered the 3D IC (IEDM 2004), where the package-level 3D IC has already been implanted in real manufacture in 2016. Unfortunately, the packaged 3D microprocessor is limited by the small interconnect density of Through-Silicon Via (TSV), which has little dynamic switching power and operation speed improvement. Besides, the huge heat-dissipation from 1000 W AI accelerator may cause 3D package fail.
In this talk, monolithic 3D IC architecture using high-mobility MOSFET (IEDM 2015), on the IC backend amorphous-SiO2, will be presented. For the first time, the SnON nanosheet nFET has electron mobility higher than single crystal Si, InGaAs, two-dimensional MoS2 and WSe2 nFETs at the same 5-nm body thickness. The SnO nanosheet nFET reached ~1/5 of crystal Si at the same 7-nm body thickness. Besides, those SnO2-SnO CMOS were fabricated by sputtering, which can be implemented into IC manufacture without the challenge of 2D materials. This monolithic 3D IC is the technology to improve the circuit speed, dynamic switching power, integration density, down-scaling cost, and performance gap to bio system. The monolithic 3D IC is especially important since the down-scaling 2D IC will soon reach the lithography limit around 2030 at 7Å node.
Date: 17th September 2025
Time: 10:00 am CET | 04:00 pm CST (Asia)
Webinar ID: 869 4069 7477
Webinar Secretariat: journal.webinar@mdpi.com
The webinar was hosted via Zoom and required registration to attend. The full recording can be found below. In order to learn about future webinars, you can sign up to our newsletter by clicking “Subscribe” at the top of the page.
3D technology is essential for improving operation speed and reducing dynamic power consumption. High-mobility oxide CMOS for 3D ICs and embedded SRAM on the VLSI backend enable 3D brain-mimicking ICs and in-memory computing. Compared to expensive sub-7nm ICs, 3D ICs offer better performance and smaller chip sizes, extending progress beyond scaling limits. Our Monolithic 3D Integration, recognized by IEDM as a future technology, is likely to be adopted in next-generation IC manufacturing—following our earlier successes in high-k CMOS, high-k flash memory, and 3D IC innovations.