Nanomaterials Webinar | Breaking Moore’s Law Barrier: Transistors for Three-Dimensional Brain-Mimicking IC Architecture
Welcome from the Chair
The delay and power consumption are the major limitation for advanced microprocessor, even though the device will soon reach Hyper-EUV lithography and quantum-mechanical downscaling limits. To address these issues, we pioneered the 3D IC (IEDM 2004), where the package-level 3D IC has already been implanted in real manufacture in 2016. Unfortunately, the packaged 3D microprocessor is limited by the small interconnect density of Through-Silicon Via (TSV), which has little dynamic switching power and operation speed improvement. Besides, the huge heat-dissipation from 1000 W AI accelerator may cause 3D package fail.
In this talk, monolithic 3D IC architecture using high-mobility MOSFET (IEDM 2015), on the IC backend amorphous-SiO2, will be presented. For the first time, the SnON nanosheet nFET has electron mobility higher than single crystal Si, InGaAs, two-dimensional MoS2 and WSe2 nFETs at the same 5-nm body thickness. The SnO nanosheet nFET reached ~1/5 of crystal Si at the same 7-nm body thickness. Besides, those SnO2-SnO CMOS were fabricated by sputtering, which can be implemented into IC manufacture without the challenge of 2D materials. This monolithic 3D IC is the technology to improve the circuit speed, dynamic switching power, integration density, down-scaling cost, and performance gap to bio system. The monolithic 3D IC is especially important since the down-scaling 2D IC will soon reach the lithography limit around 2030 at 7Å node.
Date: 17th September 2025
Time: 10:00 am CET | 04:00 pm CST (Asia)
Webinar ID: 869 4069 7477
Webinar Secretariat: journal.webinar@mdpi.com
Event Chairs
Dept. of Electronics Engineering, National Yang Ming Chiao Tung Univ., Hsinchu, Taiwan
Albert Chin received the Ph.D. degree in electrical engineering from the University of Michigan. He was with AT&T Bell Labs, General Electric Electronic-Lab, Texas Instruments SPDC, and visiting professor at National University of Singapore. He is a Life Chair Professor of National Yang Ming Chiao Tung University. He is a pioneer on low DC-power high-κ CMOS and high-κ Flash memory, low dynamic-switching-power 3D IC, monolithic 3D integration, high RF-power asymmetric MOSFET, Si THz devices, and resonant-cavity photo-detector. He has co-authored >500 papers, four “Top 100 Scientific Reports Physics papers” in 2017~2020, one “Top Articles in Device Physics of Applied Physics Letters”, cover story for Nanomaterials, and 7 Highly Cited Papers. Dr. Chin has served as Subcommittee Chair and Asian Arrangements Chair of International Electron Devices Meeting (IEDM) Executive Committee, IEEE Electron Device Letters Editor, IEEE ED Society SRC Chair, and two Technical Committee Chairs on “Electronic Materials” and “Compound Semiconductor Devices & Circuits”. He is an IEEE Life Fellow, The Optical Society Optica Fellow, Intl Assn Advanced Materials Fellow and Asia-Pacific Academy of Materials Academician and President of Taiwan chapter. He is the World's Top 2% Scientist Lifetime, Elsevier, Top Scientist in Electronics & Electrical Engineering, Research.com and Top 0.5% Scholar – Lifetime Scholar GPS.
Program
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Speaker/Presentation |
Time in CEST/CET | Time in CST Asia |
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Prof. Dr. Albert Chin Review Collection in Nanoelectronics, Nanosensors and Devices |
10:00 - 11:00 | 16:00 - 17:00 |
