As Moore's Law approaches its end and the Von Neumann architecture faces bottlenecks such as the "memory wall" and "power wall," the existing computational power is increasingly unable to meet the demands of the AI era. This necessitates a revolutionary shift in our current computing paradigms to overcome these challenges. However, traditional devices fall short of the stringent performance requirements posed by these new architectures. Therefore, we must explore novel device concepts that are better suited to emerging computational frameworks. In this talk, I will present three high-performance devices that hold promise for next-generation computing: ferroelectric tunnel junctions based on semimetal contacts that offer compatibility with silicon processes and high on/off ratios, resistive random-access memory (RRAM) with 2048 resistance states, and interface charge transfer transistors based on graphene/MoS₂ heterostructure designed for reconfigurable computing.