This study investigates the high-frequency capacitance behavior of metal/insulator/polysilicon (MIS) structures used in polycrystalline silicon (poly-Si) thin-film transistors (TFTs) through two-dimensional numerical modeling. A custom simulation code based on Poisson’s equation was developed to model the electrostatic potential and capacitance characteristics of an Al/SiO₂/poly-Si structure, accounting for the granular nature of poly-Si.
The poly-Si active layer is represented as a series of columnar grains separated by narrow, highly defective grain boundaries (GBs). These GBs, oriented perpendicular to the oxide interface, act as energy barriers that trap free carriers and reduce mobility. Simulations highlight how the number of GBs, grain size, layer thickness, and oxide thickness impact high-frequency capacitance and threshold voltage.
Results show that increasing the number of GBs shifts the capacitance–voltage C (V) curve, raising the threshold voltage due to enhanced charge trapping. Similarly, larger grain sizes and thicker active layers also lead to increased threshold voltages, with a quasi-linear relationship between grain size and layer thickness amplifying this effect. Thicker oxide layers reduce gate control, further increasing the threshold voltage.
A detailed electrostatic potential distribution confirms that GBs trap carriers and form potential barriers, especially under depletion conditions. These findings demonstrate the strong dependence of poly-Si TFT capacitance behavior on structural properties.
To optimize TFT performance, the study suggests increasing grain size and reducing GB density, which can be achieved through techniques like laser crystallization or rapid thermal annealing. These modifications lower defect density, improve carrier mobility, and enhance device performance.
In conclusion, the paper provides a valuable numerical tool and physical insights into the capacitive behavior of poly-Si TFTs, with direct implications for designing efficient electronic and display components.
