Please login first
Rapid prototyping on SOI 220 nm of integrated optical structures with polymer cladding within the QUANTEP collaboration
* 1 , 1 , 2 , 1 , 2 , 3 , 3 , 4 , 4 , 5 , 5 , 5 , 5 , 4 , 6 , 6 , 7 , 8 , 5
1  National Institute for Nuclear Physics (INFN) Pisa Division, Pisa, 56127, Italy
2  Department of Information Engineering, University of Pisa, Pisa, 56122 , Italy
3  Department of Physics, University of Modena and Reggio Emilia, Via Campi 213/a, Modena, I-41125, Italy
4  National Institute for Nuclear Physics (INFN) Roma Tor Vergata Division, Roma, 00133, Italy
5  National Institute for Nuclear Physics (INFN) Pavia Division, Pavia, 27100, Italy
6  Nanotechnology group, University of Salamanca, Plaza de la Merced, Salamanca, 37008, Spain
7  National Institute for Nuclear Physics (INFN) Perugia Division, Perugia, 06123, Italy
8  Department of Physics, University of Cagliari, Cittadella Universitaria di Monserrato, S.P. 8 km 0,700 - Monserrato (CA), 09042, Italy
Academic Editor: Andrea Salamon

Published: 20 March 2026 by MDPI in The 1st International Online Conference on Optics session Quantum Optics
Abstract:

Introduction: QUANTEP develops quantum-optics devices using silicon photonics. Foundry runs highlighted the need for in-house prototyping for fast iterations, often before final oxide encapsulation and before full optical testing is available. We present a SOI 220 nm workflow where a reversible polymer overcladding acts as a non-permanent photonic environment to accelerate early fabrication of nanowaveguides and grating couplers, compatible with post-processing such as metallization and local rework.

Methods: Patterns were defined by electron-beam lithography (EBL) on SOI 220 nm and transferred by reactive ion etching (RIE). In this first iteration, an Al hard mask improved pattern transfer; in parallel, the flow migrated toward high-etch-resistance resists (e.g., CSAR-class) to reduce complexity in subsequent runs. The design set included full-etch and partial-etch grating coupler (GC) variants: full-etch structures were obtained by RIE, while partial-etch regions were implemented locally by ion beam (FIB) milling and quantified by atomic force microscopy (AFM). Selected chips were coated with approximately 2 um polymethyl methacrylate (PMMA) to enable waveguide confinement; EBL-defined windows preserved access for alignment, metallization, and local rework while keeping polymer coverage on photonic areas. Etch depths and film thicknesses were obtained from AFM and tilted-stage SEM.

Results and Conclusions: SEM confirms fabrication of nanowaveguides and GC structures. AFM validates a partial-etch depth of 65 +/- 6 nm versus a 70 nm target and verifies PMMA thickness. The workflow provides a SOI 220 nm prototyping route combining RIE transfer, FIB partial-etch, and reversible polymer overcladding. While not replacing final SiO2 encapsulation, PMMA increases processing flexibility and enables access windows, metallization, and local rework that would be more complex with oxide cladding.

Keywords: QUANTEP; SOI220nm, cladding, pmma, EBL, FIB, workflow, RIE, full-etch, partial-etch
Top