The accurate estimation of the State of Charge in lithium-ion batteries represents a fundamental task for modern energy management systems, yet it remains a complex challenge due to latent electro-thermal dynamics that cannot be directly observed through simple terminal measurements. In this study, we present a robust and physically consistent framework that utilizes internal resistance as an intermediate variable to stabilize the prediction of the State of Charge.
The work begins with an in-depth predictive power analysis conducted on an experimental dataset. The primary objective was to evaluate the observability of the effective internal resistance based on current, voltage, and temperature statistics. The results of this preliminary analysis revealed a significant disparity in the information provided: while the mean values of current and temperature show limited correlation when considered individually, the statistical features derived from voltage, including variance and quartile distributions, carry the dominant predictive information. Furthermore, we demonstrated that the calculation of the instantaneous ratio between voltage and current variations acts as an essential physical descriptor capable of linking raw data to the electrochemical state of the cell.
Based on these findings, an extremely lightweight resistance estimator was trained, achieving a very low relative error. This component is then coupled with a lumped thermal model. The true innovation of this approach lies in the way the thermal model is utilized: instead of incorporating it as additional input data, which would increase computational complexity during real-time use, it is introduced as a regularization term within the loss function during the training phase. This method imposes electro-thermal consistency by penalizing State of Charge trajectories that deviate from the heat generation profiles predicted by the physics of Joule heating. Experimental results demonstrate that this strategy significantly improves the robustness and stability of the system under various operating conditions, while ensuring zero additional computational load for the on-board hardware during final execution.