The semiconductor industry has evolved significantly since its founding in the 1950. Primarily used electronic devices like transistors and diodes, but advancements in technology have led to more complex and powerful semiconductor devices , from printed circuit boards to a multi-million gate design i.e. a System on Chip. SoC provides faster and reliable implementation design with low cost per gate and considerably low power consumption. In addition , it offers a smaller physical size and with greater design security. Almost 70-80 percent of the total SoC design effort is spent on the functional verification. For meeting requirement the traditional simulation methods are no longer sufficient for the system level verification. This kind of verification platform which supports a mixed functional verification with both IP core level and system level. In this thesis, verification of interconnect block in a processing system is presented. The functional verification of the design is done by using system verilog and UVM . The verification process includes creation of testcases, assertions and checkers for verifying different functionality as per the design specifications. The connectivity of the interconnect to the masters and the corresponding slaves is verified by memory mapped registers. A unique functional block which is present on the interconnect to slave interface is verified by using combination of checkers and test sequences. Performance and trace monitoring of the transactions on AXI interface of the interconnect is done by programming different operational pointers and filters. Simulated results from the Synopsys - VCS tool verifies functional correctness of the design.