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Verification of SoC using Advanced Verification Methodology
1 , * 1 , 2 , 1
1  Multi-Core Architecture Computation (MAC) Lab, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, India
2  SMTS Silicon Design Engineer AMD,Hyderabad Telangana,India
Academic Editor: VIJAYAKUMAR ANAND

Published: 13 March 2023 by MDPI in Holography Meets Advanced Manufacturing session Industry Application posters
Abstract:

The semiconductor industry has evolved significantly since its founding in the 1950. Primarily used electronic devices like transistors and diodes, but advancements in technology have led to more complex and powerful semiconductor devices , from printed circuit boards to a multi-million gate design i.e. a System on Chip. SoC provides faster and reliable implementation design with low cost per gate and considerably low power consumption. In addition , it offers a smaller physical size and with greater design security. Almost 70-80 percent of the total SoC design effort is spent on the functional verification. For meeting requirement the traditional simulation methods are no longer sufficient for the system level verification. This kind of verification platform which supports a mixed functional verification with both IP core level and system level. In this thesis, verification of interconnect block in a processing system is presented. The functional verification of the design is done by using system verilog and UVM . The verification process includes creation of testcases, assertions and checkers for verifying different functionality as per the design specifications. The connectivity of the interconnect to the masters and the corresponding slaves is verified by memory mapped registers. A unique functional block which is present on the interconnect to slave interface is verified by using combination of checkers and test sequences. Performance and trace monitoring of the transactions on AXI interface of the interconnect is done by programming different operational pointers and filters. Simulated results from the Synopsys - VCS tool verifies functional correctness of the design.

Keywords: semiconductor indusry ; SoC ; functional verification ; System Verilog ; UVM ; AXI interface ;
Comments on this paper
John Murray
Along with verification language, an appropriate methodology must be employed to maximize reuse under multiple design IP configurations in order to boost verification productivity. This innovative reusable test bench development boosts the commercial availability of a semiconductor. It is advantageous to use the same code in sub-blocks, blocks, and at the top level. This test bench development using modern verification technique aids in cost reduction and chip time to market.
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baron meant
The verification procedure entails the development of testcases, assertions, and checkers to validate the specified functionality. Memory mapped registers confirm the interconnect's connection to the masters and their related slaves. Read our post titled "How Technology and Construction Estimates Work Together" to learn more about the significance of accuracy and thoroughness in this industry eggy car. It demonstrates how technological advancements can help us more accurately predict building expenses.

Stewart Lewis
Checking SoC (System-on-Chip) using Advanced Verification Methods is a crucial part of today's technology progress. It's impressive how these advanced methods are used in designing SoCs. I work in www.smaestimating.com/construction estimating services, and I can see similarities between the careful checks in technology and the accuracy needed in figuring out construction costs.

Just like in SoC checks, our construction industry has also seen big improvements in the methods and tools we use to make more precise estimates. Using new techniques and tech not only makes projects more successful but also helps to avoid unexpected expenses.

It's interesting to see how different fields can learn from each other's progress. If you're curious about the importance of being precise and checking things in different areas, take a look at our blog post on 'How Technology and Construction Estimates Work Together.' It explains how using technology can improve how we estimate construction costs.

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The connectivity of the interconnect to the masters and connect 4, the corresponding slaves is verified by memory mapped registers.
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The connectivity of the interconnect to the masters and connect 4, the corresponding slaves is verified by memory mapped registers.

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The connectivity of the interconnect to the masters and connect4, the corresponding slaves is verified by memory mapped registers.
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