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HakSun Lee  - - - 
Top co-authors
Kwang-Seong Choi

106 shared publications

ICT Materials and Components Research Laboratory; Electronics and Telecommunications Research Institute (ETRI); Daejeon South Korea

Hyun‐Cheol Bae

56 shared publications

ICT Materials and Components Research Laboratory; Electronics and Telecommunications Research Institute (ETRI); Daejeon South Korea

Yong-Sung Eom

50 shared publications

ICT Materials and Components Research Laboratory; Electronics and Telecommunications Research Institute (ETRI); Daejeon South Korea

Keon-Soo Jang

13 shared publications

ICT Materials & Components Research Laboratory, Electronics and Telecommunications Research Institute (ETRI), Daejeon 34129, South Korea

Ji‐Hye Son

5 shared publications

13
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Publication Record
Distribution of Articles published per year 
(2013 - 2015)
Total number of journals
published in
 
8
 
Publications See all
Article 4 Reads 0 Citations Internal Defect Position Analysis of a Multi-Layer Chip Using Lock-in Infrared Microscopy Seon-Jin Kim, Kye-Sung Lee, Hwan Hur, HakSun Lee, Hyun-Cheol... Published: 30 June 2015
JOURNAL OF THE KOREAN SOCIETY FOR NONDESTRUCTIVE TESTING, doi: 10.7779/jksnt.2015.35.3.200
DOI See at publisher website
Article 0 Reads 0 Citations Novel Low-Volume Solder-on-Pad Process for Fine Pitch Cu Pillar Bump Interconnection Hyun-Cheol Bae, HakSun Lee, Yong-Sung Eom, Kwang-Seong Choi Published: 30 June 2015
Journal of the Microelectronics and Packaging Society, doi: 10.6117/kmeps.2015.22.2.055
DOI See at publisher website
Article 0 Reads 1 Citation HV-SoP Technology for Maskless Fine-Pitch Bumping Process Jihye Son, HakSun Lee, Yong‐Sung Eom, Kwang‐Seong Choi, Hyun... Published: 01 June 2015
ETRI Journal, doi: 10.4218/etrij.15.0114.0578
DOI See at publisher website ABS Show/hide abstract
Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip-chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine-pitch solder bumping has been widely studied. In this study, high-volume solder-on-pad (HV-SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are 28.3 μm, 31.7 μm, and 26.3 μm, respectively. It is expected that the HV-SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine-pitch flip-chip bonding.
Conference 0 Reads 0 Citations Characterization of 3D stacked high resistivity Si interposers with polymer TSV liners for 3D RF module Kwang-Seong Choi, HakSun Lee, Hyun-Cheol Bae, Yong-Sung Eom,... Published: 01 May 2015
2015 IEEE 65th Electronic Components and Technology Conference (ECTC), doi: 10.1109/ectc.2015.7159705
DOI See at publisher website
Article 0 Reads 2 Citations Interconnection Technology Based on InSn Solder for Flexible Display Applications HakSun Lee, Kwang‐Seong Choi, Hyun‐Cheol Bae, Yong‐Sung Eom Published: 01 April 2015
ETRI Journal, doi: 10.4218/etrij.15.0114.0167
DOI See at publisher website ABS Show/hide abstract
A novel interconnection technology based on a 52InSn solder was developed for flexible display applications. The display industry is currently trying to develop a flexible display, and one of the crucial technologies for the implementation of a flexible display is to reduce the bonding process temperature to less than 150°C. InSn solder interconnection technology is proposed herein to reduce the electrical contact resistance and concurrently achieve a process temperature of less than 150°C. A solder bump maker (SBM) and fluxing underfill were developed for these purposes. SBM is a novel bumping material, and it is a mixture of a resin system and InSn solder powder. A maskless screen printing process was also developed using an SBM to reduce the cost of the bumping process. Fluxing underfill plays the role of a flux and an underfill concurrently to simplify the bonding process compared to a conventional flip-chip bonding using a capillary underfill material. Using an SBM and fluxing underfill, a 20 μm pitch InSn solder SoP array on a glass substrate was successfully formed using a maskless screen printing process, and two glass substrates were bonded at 130°C.
Article 0 Reads 1 Citation Development of Copper Electro-Plating Technology on a Screen-Printed Conductive Pattern with Copper Paste Yong-Sung Eom, Ji-Hye Son, Hak-Sun Lee, Kwang-Seong Choi, Hy... Published: 30 March 2015
Journal of the Microelectronics and Packaging Society, doi: 10.6117/kmeps.2015.22.1.051
DOI See at publisher website
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